Due to the high degree of miniaturization possible today in semiconductor technology, the size and complexity of designs that may be implemented in hardware has increased dramatically. This has made it technologically feasible and economically viable to develop high-speed applications-specific architectures featuring a performance increase over previous architectures. Process scaling has been used in the miniaturization process to reduce the area needed for logic functions in an effort to lower the product costs. Process scaling continues to improve performance but at the expense of power.
Precharged Complementary Metal Oxide Semiconductor (CMOS) domino logic techniques may be applied to functional blocks to reduce power. Domino logic forms an attractive design style for high performance designs since its low switching threshold and reduced transistor count leads to fast and area efficient circuit implementations. Thus, domino CMOS has become a prevailing logic family for many high performance CMOS applications and is used in many state-of-the-art processors due to its high speed capabilities.
However, domino logic suffers from several design problems and one of the most notable design problems is the charge-sharing problem. In domino logic there are two operational phases, a pre-charge phase and an evaluation phase. The charge-sharing problem occurs when the charge that may be stored at the output node in the pre-charge phase is shared among the junction capacitance of transistors in the evaluation phase. Charge sharing may degrade the output voltage level or even cause an erroneous output value.
One drawback of domino CMOS is that the logic is precharged making the design sensitive to power constraints. Thus, there is a continuing need for better ways to provide flexibility for operating a microprocessor, memory or other circuit having domino logic while preserving low operating currents.